(1) Field of the Invention
The present invention relates to a method for fabricating integrated circuits. More particularly, the method utilizes a novel mask design to form wider guard-band rings around the logic regions on merged DRAM circuits. This novel design prevents the formation of unwanted (superfluous) narrower guard rings that are inadvertently formed in stacked films over steps in the underlying substrate. These unwanted narrow guard rings are formed when anisotropic plasma etching is used for etching high-aspect-ratio patterns on the substrate using the conventional processes. The narrow guard rings tend to peel during subsequent processing, which causes defects. In this novel design wider guard rings are intentionally formed to prevent the peeling that would otherwise occur with the narrower guard rings.
(2) Description of the Prior Art
The integrated circuit density on ultra-large-scale integrated (ULSI) circuits has dramatically increased due to advances in semiconductor processing, such as the use of high-resolution photolithography and anisotropic plasma etching, to achieve very narrow (submicrometer images) device structures having high aspect ratios. Also the deposition of a conformal layer and anisotropic plasma etching are used in current processing to make sidewall spacers for self-aligning structures, such as the sidewall spacers on FET gate electrodes. However, in many cases the anisotropic plasma etching can result in unwanted structures on the substrate that are detrimental to the semiconductor process.
The problem associated with the narrow guard rings is best understood with reference to FIGS. 1-3 for the conventional logic/merged DRAM circuits processing. In FIG. 1 a schematic cross-sectional view is depicted for a portion of a substrate that has a logic region having FETs on the left side of the drawing, labeled L, and a memory region having DRAM cells on the right side, labeled M. The process sequence in this conventional process starts by forming shallow trench isolation 12 in a single-crystal-silicon substrate 10. Next an amorphous silicon layer 14 is deposited and patterned by masking and etching to leave a blanket portion over the logic region. A stacked polycide film (layer) 16, 18, and 20 is deposited and patterned to form the FET gate electrodes and word lines for the DRAM devices in the memory region M. The stacked layer consists of a conductively doped polysilicon layer 16, a silicide layer 18, and an upper insulating layer 20, such as silicon nitride, having an approximate stoichiometric composition of Si3N4. The stacked film (layers 16, 18, and 20) is then patterned using a photoresist etch mask 22 and anisotropic plasma etching to minimize the bias etching (lateral etching) to achieve high-resolution images in the stacked film. Unfortunately, as shown in FIG. 2, the directional etching results in unintentional sidewall spacers (or residue) 20xe2x80x2 in the Si3N4 layer 20 that then acts as a masking material when the etching is continued to pattern the remaining silicide layer 18 and the doped polysilicon layer 16, as shown in FIG. 3. Also as shown in FIG. 3, a second photoresist mask (not shown) and anisotropic etching are then used to pattern the portion of the amorphous silicon layer 14 over the logic regions to form the FET gate electrodes, also labeled 14, and to form local inter-connections. Next sidewall spacers 24 are formed on the logic FET gate electrodes 14 and the memory FET gate electrodes (layers 16, 18, and 20). The sidewall spacers 24 also form on the narrow guard ring A composed of the narrow strips of layers 16, 18, and 20xe2x80x2, also depicted in FIG. 3. These thin multilayers in the narrow guard ring result in high stress and, during subsequent processing, can result in various degrees of peeling that form particle defects and reduce the product yield.
Several methods of making guard rings around device areas to prevent contamination have been reported in the literature. For example, U.S. Pat. No. 5,926,697 to Yaung et al. shows a method for making a guard ring to prevent diffusion of moisture and contaminants from a window in an insulating layer to the semiconductor device regions. U.S. Pat. No. 5,567,643 to Lee et al. also shows a method for forming guard rings (annular metal rings) to prevent contamination from diffusing through window openings in several insulating layers. U.S. Pat. No. 5,851,870 to Alugbin et al. shows a method for making a capacitor in which contacts to the capacitor bottom electrode also form guard rings.
The narrow unwanted guard rings depicted in the prior art FIGS. 1-3 are generally a problem for making reliable integrated circuits with good yield. There is still a need in the semiconductor industry to provide an improved process for making logic/merged DRAM circuits without these narrow unwanted guard rings or to modify the guard ring to minimize the peeling problem, while providing a cost-effective manufacturing process.
It is therefore a principal object of this invention to provide a wide guard ring that extends over a step formed in the underlying substrate at the perimeter of logic regions on merged logic/DRAM circuits which prevents peeling of the narrow guard ring inadvertently formed using the more conventional processing.
Another object of this invention is to achieve the above objective by modifying the design of a photoresist etch mask for etching the salicide FET gate electrodes in a stacked film. The modified etch mask includes portions of the photoresist over the step in the underlying substrate. The photoresist portion is then used to etch wider guard rings in the stacked film over the step, which is less susceptible to peeling.
Still another object of this invention is to form the guard rings at the same time that the salicide FET gate electrodes are formed to minimize the number of photoresist masks, and therefore provide a cost-effective manufacturing process.
The method for making a wide guard ring on a merged logic/DRAM integrated circuit is achieved. This wide guard ring replaces a narrow guard ring that is unintentionally formed on the perimeter of the logic regions using the conventional process. The narrow guard ring is susceptible to peeling due to stress. This peeling results in particles on the substrate that cause defects during subsequent processing and reduces product yield.
The method for making this wider guard ring structure begins by providing a semiconductor substrate having logic regions and memory regions, both having device areas. Typically the substrate is a single-crystal silicon in which the device areas are surrounded and electrically isolated from each other by field oxide areas. For advanced high-density circuits the field oxide of choice is a shallow trench isolation consisting of a trench in the substrate that is filled with an insulating material and then polished back to form a field oxide that is planar with the substrate surface. Next a gate oxide is formed on the device areas. An amorphous silicon layer is deposited on the substrate and patterned to leave a blanket portion over the logic regions while removing portions of the amorphous layer over the memory regions. Typically the amorphous film has an etch-stop layer, such as silicon oxide and/or silicon nitride, on its top surface. Next a blanket stacked film is deposited on the substrate. Preferably the stacked film is formed by depositing consecutively a blanket polysilicon layer, a tungsten silicide layer, and a silicon nitride layer. The stacked film is then patterned using a first photoresist etch mask for etching FET gate electrodes over the memory regions. A key feature of this invention is that the photoresist mask is also designed to include a band of photoresist that extends over the edge of the amorphous silicon layer for etching wider guard rings. The photo-resist mask and anisotropic etching are used to pattern the stacked film for the FET gate electrodes in the memory region and to concurrently form the wider guard rings in the stacked film over the edge of the amorphous silicon layer. Since this novel guard ring is sufficiently wider than the unintentional guard ring that results in the prior art, the peeling is prevented. A second photoresist etch mask and plasma etching are used to form gate electrodes in the amorphous silicon layer over the logic regions. Next a conformal insulating layer is deposited and is anisotropically plasma etched back to form sidewall spacers on the FET gate electrodes formed in both the amorphous silicon and in the stacked film. Concurrently the sidewall spacers are formed on the wider guard rings. After forming these novel guard ring structures, conventional processing can be used to complete the FETs and memory devices including capacitors. Next the multilevels of electrical interconnections are made to complete the logic/merged DRAM circuits.